Overview High-speed serial link (SerDes PHY) design team is looking for experienced and talented digital designers to help with designing high-performance and low-power IPs. The SerDes digital design team consists of architects and ASIC designers, protocol experts, digital signal processing engineers, and algorithm designers who are driving the analysis and definition of next-generation high-speed serial links for Qualcomms next generation products targeted for 5G, artificial intelligence, and automotive applications. Responsibilities: 1.Participate in standard and Qualcomm proprietary high-speed serial link (SerDes PHY) architecture definition2.Apply computer architecture, digital signal processing, and algorithm design techniques for improving power, performance, and area of the IPs3.Design RTL and run full suite of ASIC design tools (lint checking, CDC, DFT, synthesis, formal verification, timing, etc.) 4.Develop detailed digital hardware design specification documents and verification plans5.Work with physical design (PD) team for physical implementation of the IPs 6.Work with design verification (DV) team to define test plans, verify the design, and fix bugs7.Work with testing team for silicon bringup and debugging All Qualcomm employees are expected to actively support diversity on their teams, and in the Company. Minimum Qualifications
Bachelor's degree in Science, Engineering, or related field.
2+ years ASIC design, verification, or related work experience.
Master's in Electrical Engineering and 3 years of industry experience or PhD in electrical engineering with experience designing high-speed digital circuits
Experience in low-power digital design
Experience in computer architecture, digital signal processing, and algorithm design
Experience working with various ASIC tools such as Design Compiler, primetime, PTPX, Modelsim, DFT compiler, Tetramax, and Spyglass.
Experience in creating tools and automation flows (in Python, Perl, or C) for improving productivity and efficiency
Experience with leading edge high-speed PHY designs such as MIPI, USB3, and PCIe Gen 2/3/4